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    • 专利摘要:

    公开号:FR3083654A1
    申请号:FR1856189
    申请日:2018-07-05
    公开日:2020-01-10
    发明作者:Yohan Joly；Vincent BINET
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    Method for polarizing the outputs of a folded cascode stage of a comparator and corresponding comparator
    Embodiments and embodiments relate to integrated circuits comprising a comparator, in particular a fast comparator.
    In a comparator circuit, two input voltages are compared and an output voltage representative of the difference between the input voltages is generated. The comparison is typically carried out using a differential pair of transistors.
    FIG. 1 represents an example of differential pairs of transistors configured to be incorporated in a comparator but having performance defects.
    The transistors of the differential pairs preferably have very close characteristics, in particular the threshold voltage, in order to ensure an accurate comparison. However, due to the manufacturing uncertainties of the transistors, it is difficult to manufacture at reasonable cost paired transistors having strictly the same characteristics. Typically, to match the transistors of a differential pair, resistive compensators 20, comprising resistive elements 21, 23 connected to the sources of the transistors of the differential pair, make it possible to apply a corrective potential to the respective sources. The corrective potential pre-polarizes the gate-source voltages of the pair's transistors so that they behave similarly in response to the input voltages IN-, IN + on their gates. This improves the input accuracy of the comparator.
    In addition, a hysteresis between the input voltages IN-, IN + is generally introduced after initiating a comparison. The hysteresis effect is used to avoid parasitic comparisons due to accidental variations, for example due to electrical noise. Typically, the hysteresis effect is obtained by modifying the conductivity of a transistor in the differential pair, biasing the input value required to trigger the transistors. For example, to modify the conductivity of a transistor, a conventional solution consists in connecting or disconnecting on command a stack of transistors 11, 12, 13, 14, 15, 16, 17 in parallel on one of the transistors of a differential pair.
    This being the case, this type of hysteresis structure 10 requires a considerable surface to be produced, and the parallel transistors 11-17 introduce a parasitic capacitance at input IN-, IN + which increases the delay in propagation of the signal in the comparator. For example, the stray capacitance, such as the gate capacitances of the transistors in parallel 11-17, can have a value greater than five times the capacitive input value without hysteresis structure 10.
    In addition, the resistive elements 21, 23 belonging to the resistive compensators 20, typically introduce a polysilicon / parasitic substrate capacitance on the sources of the transistors of the differential pairs.
    However, in comparators intended to be very efficient, in particular in terms of input-output propagation speed, these parasitic capacities are extremely harmful and difficult to reduce as they stand.
    Thus there is a need to design fast comparators whose input capacitive value is minimized, while preserving the input precision as well as the generation of a hysteresis effect.
    In this regard, there is proposed in one aspect a method of polarizing a positive output and a negative output of a folded cascode stage of a comparator, comprising:
    - a regulation of the voltages on the positive output and on the negative output comprising a circulation of a regulation current in two resistive elements respectively located between the two outputs and a common mode node having a constant common mode voltage;
    a generation of a constant and permanent compensation current in the two resistive elements, so as to compensate for a difference between effective threshold values of at least one differential pair of comparator transistors, coupled upstream of the folded cascode stage ;
    a generation, controlled by a hysteresis control signal, of a hysteresis current in the two resistive elements, so as to introduce a hysteresis offset on input values of the comparator necessary to trigger a signal of representative output of a comparison of said input values.
    In other words, it is proposed according to this aspect to implement improvements in the precision of input of the comparator and generation of hysteresis on a folded cascode stage of the comparator, not introducing any parasitic capacity slowing down the operation. . Thus, the speed of input-output of the comparator is increased, while the precision of input and the generation of hysteresis are perfectly controlled.
    According to one embodiment, the compensation current is injected on one of said positive or negative outputs via a respective cascode transistor and extracted on the other of said outputs via another transistor respective cascode.
    The cascode transistors are advantageously controlled so as to increase the output impedance of the positive and negative outputs.
    Since the compensation current can thus flow in the resistive elements in one direction or the other, it is possible to compensate for a positive difference or a negative difference between the effective threshold values of a differential pair of transistors.
    In addition, going through cascode transistors makes it possible in particular not to add parasitic capacitances on nodes of the comparator supporting variations of fast signals, and thus not to increase the propagation time of the comparator.
    According to an embodiment in which the comparator comprises two differential pairs of two respective conductivity types, the generation of the compensation current is dedicated to each type of conductivity as a function of the conductivity of the active differential pair.
    Indeed, the method according to this aspect makes it possible to compensate for any measurement of said difference, and, according to this mode of implementation, dynamically in particular applied to the differential pair in use in the comparator.
    According to one embodiment, the hysteresis control signal is the comparator output signal.
    According to an embodiment, the hysteresis current is injected on the positive output by means of a cascode transistor, and is extracted on the negative output by means of another cascode transistor.
    The cascode transistors are advantageously controlled so as to increase the output impedance of the positive and negative outputs.
    The intensity at which the hysteresis current is generated thus makes it possible to configure the amplitude of said hysteresis offset. Consequently, the amplitude of the hysteresis shift is not fixed for the same product, which can thus be adapted to different needs.
    In addition, going through cascode transistors makes it possible in particular not to add parasitic capacitances on nodes of the comparator supporting variations of fast signals, and thus not to increase the propagation time of the comparator.
    According to another aspect, an integrated circuit is proposed comprising a comparator, configured to generate an output signal representative of a comparison between input values, comprising a folded cascode stage having a positive output and a negative output, and comprising:
    - a regulating means configured to regulate voltages on the positive output and on the negative output, comprising resistive elements respectively located between each of said outputs and a common mode node configured to have a constant common mode voltage;
    a compensation means comprising at least a first current generator configured to generate a constant and permanent compensation current in the two resistive elements, so as to compensate for a difference between effective threshold values of respectively at least one differential pair of transistors of the comparator, coupled upstream of the folded cascode stage;
    a hysteresis means comprising a second current generator configured to generate, in a manner controlled by a hysteresis control signal, a hysteresis current in the two resistive elements, so as to introduce a hysteresis offset on the input values necessary to generate the comparator output signal.
    According to one embodiment, each first current generator comprises a pair of first current generator circuits, configured to respectively inject the compensation current on one of said positive or negative outputs via a respective cascode transistor and extract the compensation current on the other of said outputs via another respective cascode transistor.
    The cascode transistors are advantageously intended to be controlled so as to increase the output impedance of the positive and negative outputs.
    According to an embodiment in which the comparator comprises two differential pairs of two respective types of conductivity, the compensation means is configured to generate a compensation current dedicated to each type of conductivity controlled by a control signal representative of the conductivity of the active differential pair.
    For example, said hysteresis control signal is the comparator output signal.
    According to one embodiment, the hysteresis means comprises a pair of second current generators, configured to respectively inject the hysteresis current on the positive output via another cascode transistor and extract the hysteresis current on the negative output via another cascode transistor.
    The cascode transistors are advantageously intended to be controlled so as to increase the output impedance of the positive and negative outputs.
    Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and implementation, in no way limiting, and the appended drawings in which:
    - Figure 1, previously described, shows a differential pair of transistors which may belong to a conventional comparator;
    - Figures 2 to 7 illustrate examples of embodiments and implementation of the invention.
    FIG. 2 represents an example of an integrated circuit CI comprising a comparator CMP, configured to generate a signal VCOMP at a first voltage level (logic "1") when the level of a positive input voltage IN + exceeds the level of a negative input voltage IN-.
    The CMP comparator comprises a differential preamplification stage PAD, receiving the positive and negative input voltages on respective inputs IN +, IN- called positive input and negative input respectively.
    FIG. 3 represents an example of the PAD differential preamplification stage and a power supply device configured to supply a bias current Ib to the PAD stage.
    The PAD differential preamplification stage has two differential pairs of transistors. A differential pair called conduction P comprises two PMOS transistors MP +, MP-, the sources of which are coupled to a polarization node of conduction P, IBP. The other differential pair, called the N conduction pair, has two NMOS transistors MN +, MN-, whose sources are coupled to an N conduction polarization node IBN.
    The gates of the transistors MP +, MN + are coupled to the positive input IN +, while the gates of the transistors MP-, MN- are coupled to the negative input IN-. The drains of each transistor form a respective intermediate output called conduction P and conduction N, respectively referenced OUTP +, OUTP-, OUTN +, OUTN-.
    The PAD preamplification stage is supplied by a bias current Ib generated by a bias current generator IbGEN. The bias current Ib is applied either to the conduction bias node P, IBP, or to the conduction bias node N, IBN. The bias current Ibb flowing on the node IBN comes from a current mirror circuit Cp configured to copy the bias current Ib exiting from the bias current generator IbGEN to the conduction bias node N IBN. The current mirror assembly Cp comprises a MOS transistor mounted as a diode Md and a copy MOS transistor Mc controlled by the gate voltage of the MOS transistor mounted as a diode Md.
    The current mirror assembly Cp is coupled to the bias current generator IbGEN by means of an MOS transistor MSW controlled by a CASCN signal giving it a switch function. The transistor MSW and the signal CASCN are configured so that the voltage VgsMSW between the gate and source terminals of the transistor MSW automatically switches the transistor MSW in the event of conduction P or N in the respective differential pairs MP + / MP-, MN + / MN-.
    In the PAD differential preamplification stage, no additional element introduces parasitic capacitance on nodes carrying the differential signals of the CMP comparator.
    Again with reference to FIG. 2, the differential preamplification stage PAD is coupled upstream of a folded cascode stage CASCR (or "folded cascode" according to the usual English term).
    The folded cascode stage CASCR receives the signals on the four intermediate outputs OUTN +, OUTN-, OUTP +, OUTP- from the differential pairs MP + / MP-, MN + / MN- of the differential preamplification stage PAD.
    The folded cascode stage CASCR comprises a first branch BRI and a second branch BR2 which are symmetrical and configured to generate two differential output signals VOUT-, VOUT + (FIG. 7) on respective differential output nodes OUT-, OUT +, from the four intermediate outputs of the PAD differential preamplification stage.
    By convention in this example, the elements belonging to the first branch BRI, on which the negative differential output signal OUT- is generated, are designated by an odd reference, for example MPI or MN3. The elements belonging to the second branch BR2, on which the positive differential output signal OUT + is generated, are designated by an even reference, for example MP2, or MN4.
    Each branch has a PMOS transistor MPI, MP2 current generation, controlled by a BIASP signal to flow a current in each branch from a VDD supply terminal.
    PMOS transistors MP3, MP4 cascodes are coupled between the current generation transistors MPI, MP2 and the respective output nodes OUT-, OUT +. The MP3, MP4 cascode transistors are controlled by a CASCP cascode signal to increase the output impedance and thus reduce the variations in current compared to the drain voltage. Thus, for any variation, in particular of the VDD power supply, the current generation transistors MPI, MP2 have the same drain potential in order to generate a stable current.
    Each branch includes a NMOS current mirror transistor MN1, MN2, coupled between a reference voltage terminal GND and the respective differential output nodes OUT-, OUT +, by means of cascade NMOS transistors MN3, MN4 controlled by a cascode signal CASCN, analogously to PMOS transistors MP3, MP4 cascodes.
    Each NMOS current mirror transistor MN1, MN2 is configured to copy a current flowing in the branch of the other current mirror transistor. Indeed, the gates of the mirror transistors MN1, MN2 are coupled on a common mode node MCbias, resistively coupled to each output node OUT-, OUT +.
    A respective resistive element RI, R2 is located between each of said outputs OUT-, OUT + and the common mode node MCbias.
    It is specified here that the nature of the current mirror assembly MN1, MN2 imposes a constant voltage on the common mode node MCbias, called common mode voltage MCbias.
    With reference to FIGS. 2 and 3, the intermediate positive N conduction output OUTN +, coming from the drain of the transistor MN + of the conduction N controlled by the positive input IN +, is coupled to the output (drain) of the current generation transistor MP2 of the second branch BR2 of the folded cascode assembly CASCR.
    The intermediate negative conduction output N OUTN-, coming from the drain of the transistor MN- of conduction N controlled by the negative input IN-, is coupled to the output (drain) of the current generation transistor MPI of the first branch BRI of the cascode assembly folded CASCR.
    The intermediate positive P conduction output OUTP +, coming from the drain of the MP conduction transistor P + controlled by the positive input IN +, is coupled to the output (drain) of the current mirror transistor MN 1 of the first branch BRI of the folded cascode assembly CASCR.
    The intermediate conduction output P positive OUTP-, coming from the drain of the transistor MP- conduction P controlled by the negative input IN-, is coupled to the output (drain) of the current mirror transistor MN2 of the second branch BR2 of the assembly CASCR folded cascode.
    Thus, in N conduction, a given distribution of the bias current Ibb is taken from the drains of the current generation transistors MPI, MP2. Said given distribution of the sampled current comes directly from the respective conductivities of the transistors MN + / MN- of the differential pair of conduction N.
    In P conduction, a given distribution of the bias current Ib is injected into the drains of the current mirror transistors MN1, MN2. Said given distribution of the injected current comes directly from the respective conductivities of the MP + / MP- transistors of the differential conduction pair P.
    The difference between resulting currents, at the level of the differential outputs OUT-, OUT +, in the first branch BRI and in the second branch BR2, is forced to be balanced by the effect of the current mirror assemblies of the transistors MN1, MN2. Thus, a regulation current flows through the resistive elements RI, R2 on the common mode node MCBias and between the two outputs OUT-, OUT +.
    The resistive elements RI, R2 are polarized by flow of the regulation current and voltages are generated at their terminals. However, the common mode node MCBias is at a constant potential by nature of the current mirror assembly MN1, MN2. This potential is called MCBias common mode voltage.
    Thus, the voltages on the positive output OUT + and on the negative output OUT- are increased or decreased, inversely to each other, when the regulation current by resistive effect flows in the resistive elements RI, R2.
    The regulation current is caused by sampling or injection into the branches BRI, BR2 of currents directly caused by the differences in conductivities of the transistors of the differential preamplification stage PAD, controlled by the positive input signals IN + and negative input IN-.
    In other words, as illustrated in FIG. 7, the differential output voltages VOUT +, VOUT- (dotted line here) approach and deviate from a common mode voltage MCBias, proportional to the difference between the voltage positive input VIN + and negative input voltage VIN-, In this representation, the common mode voltage MCBias would be located at the intersection of the output signals VOUT +, VOUT-.
    Again with reference to FIG. 2, it has been seen that the resistive elements RI, R2, in collaboration with the current mirror transistors MN1, MN2, make it possible to generate the output voltages
    VOUT +, VOUT-, self-regulated on a common mode voltage MCBias.
    Thus, in this example, the resistive elements RI, R2 and the common mode node MCBias, configured to have a constant common mode voltage thanks to the current mirror transistors MN1, MN2, together form a regulation means 300 configured to regulate voltages on the positive output OUT + and on the negative output OUT-.
    Furthermore, an OUT output stage, such as an all-or-nothing comparator, receives the outputs OUT-, OUT + of the folded cascode assembly CASCR, and makes it possible to generate an output signal VCOMP, for example a step signal when the positive output voltage OUT + exceeds the negative output voltage OUT-, in particular as in the example illustrated in FIG. 7.
    In addition, the integrated circuit CI comprises a compensation means 210, 220 and a hysteresis means 100, making it possible respectively to compensate for input inaccuracies and to generate a hysteresis without harming the operating speed of the CMP comparator.
    Indeed, as illustrated in FIG. 3, the inputs IN +, IN- do not undergo parasitic capacitive elements in the differential preamplifier PAD.
    Reference is now made to FIG. 4.
    The hysteresis means 100 is configured to offset by a Vhyst offset, the voltages on the positive output OUT + and on the negative output OUT-.
    In this regard, the hysteresis means 100 comprises a current generator 101, configured to inject a hysteresis current Ihyst into the second branch BR2 of the folded cascode assembly CASCR. The hysteresis means 100 also includes a current generator 102 configured to extract a current equal to the hysteresis current Ihyst from the first branch BRI of the folded cascode assembly CASCR.
    For example, the hysteresis current Ihyst is injected at the drain of the current generator transistor MP2, and is extracted at the drain of the current mirror transistor MN1. In other words, the hysteresis current Ihyst is injected on the positive output OUT + via the cascode transistor MP4, and extracted on the negative output OUT- via the cascode transistor MN3.
    Thus, the hysteresis current Ihyst is forced to pass through the two resistive elements RI, R2 located respectively between each differential output OUT +, OUT- and the common mode node MCBias.
    The hysteresis current Ihyst flows in the two resistive elements RI, R2 in the same direction, in this example in the direction of the negative differential output OUT- towards the positive differential output OUT +.
    The hysteresis current thus polarizes the resistive elements RI, R2 which generate a voltage Vhyst at their terminals. The common mode voltage MCBias being constant, a shift Vhyst of the voltages on the positive output OUT + and on the negative output OUT- is thus introduced by means of hysteresis.
    Thus, the hysteresis offset is introduced so as to decrease the voltage on the negative output OUT- and increase the voltage on the positive output OUT +.
    The hysteresis current generators 101, 102 can be controlled by a hysteresis control signal ComHyst such as for example the output signal VCOMP.
    FIG. 7 illustrates (in solid lines) the positive output voltages VOUT + and negative VOUT-, with the effect of the offset DecHyst introduced by the hysteresis means 100.
    The hysteresis offset DecHyst on said output voltages VOUT +, VOUT- introduces an offset on the values of the input voltages VIN +, VIN- necessary to trigger generation of the output signal VCOMP.
    Indeed, as illustrated in FIG. 7, the positive input voltage VIN + must be at least one offset Δ Vhyst lower than the negative input voltage VIN- to equalize the differential output voltages VOUT +, VOUT-, Une Once the differential output voltages VOUT +, VOUT- have been equalized, the step of output voltages VCOMP drops to a low level, and commands the halting of the generation of the hysteresis offset DecHyst.
    Reference is now made to FIG. 5.
    The compensation means 210, 220 is configured to adjust a difference between the voltages on the positive OUT + and negative OUT- outputs, comprising at least one current generator configured to generate a constant and permanent compensation current in the two resistive elements RI, R2.
    The compensation means 210, 220 is for example intended to compensate for a difference between effective threshold values of the differential pairs of transistors MN + / MN-, MP + / MP-, of the differential preamplifier upstream of the folded cascode stage CASCR of the comparator CMP .
    In other words, if the effective threshold values of the pairs of transistors are not identical, then the comparator can trigger an output signal VCOMP while the input signals are not equal. Thus there is a gap between the IN + and IN- inputs, usually designated by the English term "offset".
    Here, the compensation of the effective threshold values of the pairs of transistors amounts to refining the offset between the positive inputs IN + and negative IN-. This allows for a more precise comparison.
    Now the compensation of the effective threshold values must be dedicated to each of the two differential pairs, that is to say for the pair of conduction P and for the pair of conduction N, independently.
    In addition, the compensation of the effective threshold values dedicated to each pair can be carried out by moving the differential output voltages OUT +, OUT- away, positively or negatively with respect to each other, depending on the effective values of a given achievement.
    Thus, the compensation means comprises a positive offset compensation means 210, configured to increase the positive output voltage OUT + relative to the negative output voltage OUT-, and a negative offset compensation means 220, configured to decrease the positive output voltage OUT + compared to the negative output voltage OUT-.
    The positive offset compensation means 210 comprises two current generators 212, 214 intended to operate in collaboration to compensate for the effective threshold voltages of the transistors of the differential conduction pair N, as well as two analog current generators 211, 213 and intended to operate in collaboration to compensate for the effective threshold voltages of the transistors of the differential conduction pair P.
    Similarly, the negative offset compensation means 220 includes two current generators 222, 224 intended to operate in collaboration to compensate for the effective threshold voltages of the transistors of the differential conduction pair N, as well as two current generators 221 , 223 analogs and intended to operate in collaboration to compensate for the effective threshold voltages of the transistors of the differential pair of conduction P.
    For example, the positive compensation means 210 comprises a current generator 211 configured to inject a positive offset compensation current Ioff + P into the first branch BRI of the folded cascode assembly CASCR. The positive compensation means 210 also comprises a current generator 213 configured to extract an equal offset compensation current Ioff + P equal from the second branch BR2 of the folded cascode assembly CASCR.
    For example, the compensation current Ioff + P is injected at the drain of the current generator transistor MPI, and is extracted at the drain of the current mirror transistor MN2. In other words, the compensation current Ioff + P is injected on the negative output OUT- via the cascode transistor MP3, and extracted on the positive output OUT + via the cascode transistor MN4.
    The current Ioff + P allows in this example to compensate the threshold values of the transistors of the differential pair of conduction P.
    Two current generators 212, 214 connected like the aforementioned current generators 211, 213, make it possible to compensate the threshold values of the transistors of the differential pair of conduction N.
    The compensation currents Ioff + P, Ioff + N are forced to pass through the two resistive elements RI, R2 located respectively between each differential output OUT +, OUT- and the common mode node MCBias.
    The compensation currents Ioff + P, Ioff + N flow in the two resistive elements RI, R2 in the same direction, in this example in the direction of the positive differential output OUT + towards the negative differential output OUT-.
    The compensation currents Ioff + P, Ioff + N thus polarize the resistive elements RI, R2 which generate a voltage Voff + at their terminals. The common mode voltage MCBias being constant, a negative offset Voff + of the voltage on the positive output OUT + and a positive offset Voff + on the negative output OUT- are thus introduced by the compensation means.
    Each pair of current generators 211/213, and 212/214 of the positive offset compensation means 210 are controlled by a SCOND signal according to the type of conductivity of the active differential pair.
    When the input voltages IN +, IN- are such that it is the differential pair of conductivity P which is conductive, then the signal SCOND controls the generators 211/213, while when it is the differential pair of conductivity N which is conductive, the SCOND signal controls the 212/214 generators.
    For example, the signal SCOND can be generated digitally, or by a comparator receiving the voltages at inputs IN +, IN-, or even come from the switching transistor MSW described previously in relation to FIG. 3.
    FIG. 6 represents the negative offset compensation means 220, comprising two current generators 221, 223 intended to operate in collaboration to compensate the effective threshold voltages of the transistors of the differential conduction pair P, as well as two current generators 222, 224 analogous and intended to operate in collaboration to compensate for the effective threshold voltages of the transistors of the differential pair of conduction N.
    The negative offset compensation means 220 has a function opposite to that of the positive offset compensation means 210, introducing a positive offset Voff- of the voltage on the positive output OUT + and a negative offset Voff- on the negative output OUT -, and is located at the same place of the CASCR folded cascode assembly as the hysteresis means.
    It is added that all the current generators 211, 212, 213, 214, 221, 222, 223, 224 belonging to the compensation means 210, 220, are configured to generate a current whose intensity is dedicated to each material manufacture of the differential pairs and the actual value of their threshold voltages. For example, measurements and adjustments of said current generators are carried out in this regard during a calibration phase of the manufacture of the integrated circuit CI.
    On the other hand, the hysteresis current generators 101, 102 can also be configurable so that different values of the hysteresis offset can be applied to the same integrated circuit IC.
    Due to constraints in the realization of the compensation and hysteresis means, the intensities of the compensation and hysteresis currents may be adjusted according to bearing values whose pitch is fixed at the manufacturing of the integrated circuit.
    In addition, it is advantageous that the current generators 101, 102, 211, 212, 213, 214, 221, 222, 223, 224 belonging to the hysteresis means 100 and to the compensation means 210, 220 are coupled to the positive outputs. OUT + and negative OUT- via said respective cascode transistors MP3, MP4, MN3, MN4, in particular so as not to add capacitive elements, coming from the circuits of the current generators, directly on said outputs OUT +, OUT-.
    In fact, the rapid variations in the output voltages VOUT +, VOUT- come from the regulation current flowing in two resistive elements RI, R2, but this regulation current does not circulate beyond the conduction terminals of the cascode transistors MP3, MP4,
    MN3, MN4. Indeed, the drains of the current generation transistors MPI, MP2 and of the current mirror transistors MN1, MN2 support almost no variations, by the flow play of the currents in the symmetrical branches BRI, BR2 of the folded cascode 5 stage CASCR.
    Consequently, this functionally makes it possible not to add parasitic capacitances on nodes of the comparator supporting variations of fast signals, and thus not to increase the propagation time of the comparator.
    权利要求:
    Claims (10)
    [1" id="c-fr-0001]
    1. Method for polarizing a positive output (OUT +) and a negative output (OUT-) of a folded cascode stage (CASCR) of a comparator (CMP), comprising:
    - a regulation of the voltages on the positive output (OUT +) and on the negative output (OUT-) comprising a circulation of a regulation current in two resistive elements (RI, R2) respectively located between the two outputs (OUT +, OUT- ) and a common mode node (MCBias) having a constant common mode voltage;
    - a generation (210, 220) of a constant and permanent compensation current (Ioff +, loff-) in the two resistive elements (RI, R2), so as to compensate for a difference between effective threshold values of at least one differential pair of transistors (MN / MN +, MP + / MP-) of the comparator (CMP), coupled upstream of the folded cascode stage (CASCR);
    - a generation (100), controlled by a hysteresis control signal (ComHyst), of a hysteresis current (Ihyst) in the two resistive elements (RI, R2), so as to introduce a hysteresis offset on input values (IN +, IN-) of the comparator necessary to trigger an output signal (VCOMP) representative of a comparison of said input values (IN +, IN-).
    [2" id="c-fr-0002]
    2. Method according to claim 1, in which said compensation current (Ioff +, loff-) is injected on one of said positive (OUT +) or negative (OUT-) outputs, via a respective cascode transistor ( MP3, MP4) and is extracted on the other of said outputs (OUT +, OUT-) via another respective cascode transistor (MN4, MN3).
    [3" id="c-fr-0003]
    3. Method according to one of the preceding claims, the comparator (CMP) comprising two differential pairs (MN + / MN-, MP + / MP-) of two respective conductivity types, in which the generation of the compensation current (210, 220 ) is dedicated to each type of conductivity as a function (SCOND) of the conductivity of the active differential pair (MN + / MN-, MP + / MP-).
    [4" id="c-fr-0004]
    4. Method according to one of the preceding claims, wherein said hysteresis control signal (ComHyst) is said output signal (VCOMP).
    [5" id="c-fr-0005]
    5. Method according to one of the preceding claims, wherein said hysteresis current (Ihyst) is injected on the positive output (OUT +) via a cascode transistor (MP4) and extracted on the negative output (OUT -) via another cascode transistor (MN3).
    [6" id="c-fr-0006]
    6. Integrated circuit comprising a comparator (CMP), configured to generate an output signal (VCOMP) representative of a comparison between input values (IN +, IN-), comprising a folded cascode stage (CASCR) having an output positive (OUT +) and a negative output (OUT-), and comprising:
    - a regulating means (300) configured to regulate voltages on the positive output (OUT +) and on the negative output (OUT-), comprising resistive elements (RI, R2) respectively located between each of said outputs (OUT +, OUT- ) and a common mode node (MCBias) configured to have a constant common mode voltage;
    - a compensation means (210, 220) comprising at least a first current generator (211, 212, 213, 214) configured to generate a constant and permanent compensation current (Ioff +, loff-) in the two resistive elements (RI , R2), so as to compensate for a difference between effective threshold values of respectively at least one differential pair of transistors (MN + / MN-, MP + / MP-) of the comparator (CMP), coupled upstream of the folded cascode stage (CASCR);
    - a hysteresis means (100) comprising a second current generator (101, 102) configured to generate, in a manner controlled by a hysteresis control signal (ComHyst), a hysteresis current in the two resistive elements ( RI, R2), so as to introduce a hysteresis offset (Vhyst) on the input values (IN +, IN-) necessary to generate the output signal (VCOMP) of the comparator (CMP).
    [7" id="c-fr-0007]
    7. The integrated circuit according to claim 6, wherein each first current generator (210, 220) comprises a pair of first current generator circuits (211, 212, 213, 214), configured to respectively inject the compensation current on the 'one of said positive (OUT +) or negative (OUT-) outputs via a respective cascode transistor (MP3, MP4) and extract the compensation current on the other of said outputs (OUT +, OUT-) by intermediary of another respective cascode transistor (MN3, MN4).
    [8" id="c-fr-0008]
    8. Integrated circuit according to one of claims 6 or 7, the comparator (CMP) comprising two differential pairs (MN + / MN-, MP + / MP-) of two respective conductivity types, in which the compensation means (210, 220) is configured to generate a compensation current dedicated to each type of conductivity controlled by a control signal (SCOND) representative of the conductivity of the active differential pair (MN + / MN-, MP + / MP-).
    [9" id="c-fr-0009]
    9. Integrated circuit according to one of claims 6 to 8, wherein said hysteresis control signal (ComHyst) is said comparator output signal (VCOMP) (CMP).
    [10" id="c-fr-0010]
    10. Integrated circuit according to one of claims 6 to 9, wherein said hysteresis means (100) comprises a pair of second current generators (101, 102), configured to respectively inject the hysteresis current on the output positive (OUT +) via a cascode transistor (MP4) and extract the hysteresis current on the negative output (OUT-) via another cascode transistor (MN3).
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    FR3082017A1|2019-12-06|METHOD FOR POLARIZING AT LEAST ONE DIFFERENTIAL PAIR OF TRANSISTORS AND CORRESPONDING INTEGRATED CIRCUIT
    FR3097387A1|2020-12-18|Method of biasing a differential pair of transistors, and corresponding integrated circuit
    同族专利:
    公开号 | 公开日
    US20200014376A1|2020-01-09|
    FR3083654B1|2021-04-02|
    US10630274B2|2020-04-21|
    CN210137307U|2020-03-10|
    CN110690878A|2020-01-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    EP0594305A1|1992-10-22|1994-04-27|Advanced Micro Devices, Inc.|Comparator circuit|
    US6970022B1|2003-09-18|2005-11-29|Lattice Semiconductor Corporation|Controlled hysteresis comparator with rail-to-rail input|
    US20120015617A1|2010-07-16|2012-01-19|Qualcomm Incorporated|Squelch Detection Circuit and Method|
    US20130082778A1|2011-09-30|2013-04-04|Stmicroelectronics Pvt. Ltd.|Differential amplifier|
    IT1241394B|1990-12-31|1994-01-10|Sgs Thomson Microelectronics|COMPARATOR CIRCUIT WITH PRECISION HYSTERESIS AND HIGH INPUT IMPEDANCE|
    TWI226751B|2003-09-02|2005-01-11|Prolific Technology Inc|Hysteresis circuits used in comparator|JP2019075759A|2017-10-19|2019-05-16|ザインエレクトロニクス株式会社|Transmission device and transmission/reception system|
    FR3097387B1|2019-06-11|2021-05-28|St Microelectronics Rousset|Method of biasing a differential pair of transistors, and corresponding integrated circuit|
    法律状态:
    2019-06-20| PLFP| Fee payment|Year of fee payment: 2 |
    2020-01-10| PLSC| Search report ready|Effective date: 20200110 |
    2020-06-23| PLFP| Fee payment|Year of fee payment: 3 |
    2021-06-23| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1856189|2018-07-05|
    FR1856189A|FR3083654B1|2018-07-05|2018-07-05|POLARIZATION METHOD OF THE OUTPUTS OF A FOLDED CASCODE STAGE OF A COMPARATOR AND CORRESPONDING COMPARATOR|FR1856189A| FR3083654B1|2018-07-05|2018-07-05|POLARIZATION METHOD OF THE OUTPUTS OF A FOLDED CASCODE STAGE OF A COMPARATOR AND CORRESPONDING COMPARATOR|
    US16/449,700| US10630274B2|2018-07-05|2019-06-24|Method for biasing outputs of a folded cascode stage in a comparator and corresponding comparator|
    CN201920995898.9U| CN210137307U|2018-07-05|2019-06-28|Integrated circuit and circuit|
    CN201910577414.3A| CN110690878A|2018-07-05|2019-06-28|Method for biasing the output of a folded cascode stage in a comparator and corresponding comparator|
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